A conventional RF transmitter typically includes a baseband digital signal processor (DSP), two digital-to-analog converters (DAC), low pass filters (LPF) for quadrature channels, a quadrature modulator, a variable gain amplifier (VGA) and a power amplifier (PA). In this architecture, the quadrature modulator is operated at a relatively low level to maintain linearity while the VGA and PA are used to deliver the required RF power level. To modulate the baseband signals to a carrier RF signal and transmit over the air, the transmitter also needs quadrature clocks at the carrier frequency, DAC conversion reconstruction clocks and a control clock. Non-linearity in the components included in the RF transmitter creates harmonic distortions and inter-modulation products. These unwanted frequency components can cause spurious emissions and interference to neighboring receivers or the receiver associated with the RF transmitter, e.g. in transceiver structures.
To avoid such interference, the linearity requirements for the LPFs, quadrature modulator and VGA are very high, increasing the design complexity of these components. High linearity usually implies high power consumption, as the affected analog components operate as class A devices, resulting in a poor power efficiency. In addition, active and passive components, such as filter capacitors and large transistors for minimizing flicker noise, occupy additional silicon area which increases cost. Furthermore, analog circuits are much sensitive to process, temperature and supply voltage variation. Device matching is also a problem for deep submicron CMOS.
To relax the design difficulty associated with analog circuits and reduce area and power consumption, some conventional RF transmitters merge the DAC, LPF, quadrature modulator and VGA functions together into a digital cell. The resulting digital quadrature modulator utilizes DSP and other digital techniques to perform baseband signal processing, such as gain setting, over-sampling, interpolation and low pass filtering. In the final stage of a conventional digital quadrature modulator, the carrier clock signals are modulated by digital baseband signals and converted into modulated RF signals. Because the digital baseband signals have smaller distortion than their analog counterparts, depending on the digital signal processing accuracy or word length which is normally enough, linearity is improved. In addition, area occupation may be smaller than the equivalent analog components because large capacitors are not needed.
However, a conventional digital quadrature modulator does not include the power amplifier component of an RF transmitter, and it needs an additional power amplifier to reach the required power level. This creates redundant areas in the modulator and the power amplifier when considering the entire area of the modulator, pads and power amplifier. In addition, conventional digital quadrature modulators typically drive a 50 Ohm impedance and thus power consumption tends to be relatively high at the modulator output. Also, the power efficiency of the modulator and power amplifier tends to be lower because both components typically operate linearly in class A mode. Operating the modulator and power amplifier in class A mode results in constant power consumption, resulting in very low power efficiency at low output signal levels. Non-linear distortion is also difficult to compensate for in conventional power amplifiers, which gives rise to additional interference in the radio band. Since a power amplifier is not typically included as part of a conventional digital quadrature modulator, system integration is not optimized which further increases the cost of the final RF transmitter structure.